//功能：脉冲计数器模块
module pulse_cnt#(
parameter DWIDTH = 1
)(
    input clk,
	 input rst_n,
	 input pulse,
	 output reg [DWIDTH-1:0] ocnt
);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
    ocnt <= 'd0;
else
    ocnt <= pulse?ocnt+1'b1:ocnt;
end
endmodule 